The invention relates to a method for fabricating a surface-wide membrane mask on the basis of an existing or subsequently fabricated multi-layer semiconductor/insulator/semiconductor-carrier-layer substrate (SOI substrate), whereby the semiconductor layer is structured by the formation of mask openings, and the semiconductor layer and insulator layer are eroded at least in the region beneath the mask openings, so that there emerges a membrane which is formed by the structured semiconductor layer and held by a bearing ring.
In current semiconductor technology, the structuring of the silicon wafer is carried out almost entirely by lithography, with a resist pattern first being generated on the wafer in a radiation-sensitive resist layer, which pattern then serves as the mask in a subsequent processing step, i.e. an etching step. The resist mask is then removed. The resist pattern itself is likewise produced with the aid of a mask that is suitable for the respective exposure technique. In conventional photolithography, chrome masks (reticles) are employed for this, which consist of a glass plate as the carrier and a thin structured chrome layer. Masks for X-ray lithography only allow mask carrier thicknesses in the micrometer range, even when weakly absorbent materials such as silicon are utilized. This is realized by membrane masks, which consist of a central active region wherein they are thinned to the membrane and a support margin (support ring) in the original thickness of the silicon substrate. In X-ray masks, a geometrically structured absorber layer is deposited on the membrane layer.
Electron and ion lithography require membrane masks wherein the mask openings are generated not on the membrane layer but in it. The membrane layer, whose thickness is in the micrometer range, contains mask openings or holes corresponding to the figures that are to be lithographically generated. These shadow masks (stencil masks), as they are called, are mechanically relatively unstable formations, as are all membrane masks.
For electron and ion projection lithography as well as newer versions of X-ray lithography, membrane masks must be produced with thicknesses in the micrometer range and with membrane areas of up to more than 100 sq. centimeters. The membrane mask s generated by the inventive method can generally be applied in lithography procedures with charged particles and photons. An example is their application in 13 nm lithography (so-called soft X-raying). They can also be applied for masking with respect to neutral particles (atom lithography) and in all applications with an evaporation mask. Membrane masks as products of the inventive method can also be generally used for sensors.
Presuming silicon disks as the substrate material, two different technological processing variants are followed for fabricating the membrane masks. They differ principally as to whether the processing steps for mask structuring occur before (wafer flow process) or after (membrane flow process) the membrane fabrication.
In the wafer flow process as it is represented in published international PCT application WO 99/49365, the mask structures are first generated on a compact silicon wafer, and the membrane fabrication by back-etching the substrate takes place at the end of the process. On the one hand, that variant makes it possible to execute the structuring process for the mask structure on stable, more manageable wafers. On the other hand, that variant also makes very high demands on the membrane etching process, because the structured membrane side must be protected from an etch attack with absolute certainty. A boron doping of the membrane layer has been customarily provided as the etch stop technique, which often does not produce sufficiently precisely defined relations. Besides this, (homogenous) mechanical tensions in the membrane layer emerge owing to the boron doping, which can be entirely or partly compensated by an additional germanium doping. Recently, SOI (silicon on insulator) substrates have also been utilized for this reason, which are likewise described in WO 99/49365. The buried oxide layer in the SOI wafer serves as a defined etch stop, and the doping of the membrane layer can be selected arbitrarily according to other factors.
For the position of the structures that are incorporated in the membrane which are decisive for the function of the mask, a positional precision of a few nanometers is required. Even small inhomogeneities in the starting material can make it impossible to achieve this object. The underlying problem of the invention will be described below in reference to the SOI wafer flow process.
Presuming a semiconductor/insulator/semiconductor-carrier-layer substrate, the future structure of the membrane is transferred into the top semiconductor layer, i.e. the future membrane layer. In a further step, the semiconductor carrier layer is removed from the bottom side to an outer ring. Lastly, the exposed insulator layer is also removed in the center region, so that the exposed center region, which is stretched by the support ring, of the semiconductor layer lying thereon represents the structured membrane. Depending on the (homogenous) internal stress of the membrane layer, more or less intensive shifting of the mask structures occurs relative to the original position. Superimposed on this is yet another shift, which is attributable to mechanical irregularities in the semiconductor layer. While the former can be compensated if the stress is known by a predistortion of the data in the structure transfer, no such corrective possibilities exist for the latter.
The inhomogeneous stresses, which, in the extreme case, can already exert a distorting effect in the transfer of the structures into the membrane layer, arise particularly in connection with SOI substrates, for various reasons having to do with their structure or the fabrication process. For instance, the fabrication of buried oxide layers by means of wafer bonding is practically inevitably accompanied by mechanical irregularities expressing themselves in inhomogeneous stresses in the top semiconductor layer, which is often only fractions of a micrometer thick.
It is accordingly an object of the invention to provide a method of fabricating positionally exact, large area membrane masks, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which allows the fabrication of positionally exact membrane masks even when SOI substrates are utilized.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of producing a surface-wide membrane mask, which comprises:
providing an SOI substrate formed of a semiconductor layer, an insulator, and a semiconductor carrier layer;
at least partially converting inhomogeneous mechanical stresses in the semiconductor layer into a homogenous state, to thereby either provide an additional layer structure on an existing SOI substrate, or a modified layer structure in the fabrication of the SOI substrate, or both;
subsequently structuring the semiconductor layer by forming therein mask openings; and
removing the semiconductor carrier layer and the insulator layer in a region underneath the mask openings, to form a membrane structure having the structured semiconductor layer held by a support ring.
In other words, the invention may be defined as an improvement in a method of producing a surface-wide membrane mask based on an existing or yet to be produced multilayer substrate having a semiconductor layer, an insulator, and a semiconductor-carrier-layer, wherein the semiconductor layer is structured by forming mask openings therein, and the semiconductor carrier layer and the insulator layer are removed in a region s beneath the mask openings, to thereby form a membrane with the structured semiconductor layer held by a support ring. The improvement comprises:
at least partially converting inhomogeneous mechanical stresses in the semiconductor layer into a homogenous state prior to the structuring of the semiconductor layer, to thereby form either one or both of an additional layer structure on an existing SOI substrate, and a modified layer structure in the fabrication of the SOI substrate.
That is, the objects are inventively achieved in a method of the above type in that the inhomogeneous mechanical stresses in the semiconductor layer are at least partly converted into a homogenous state prior to its structuring, whereby either an additional layer structure is provided on an existing SOI substrate, or a modified layer structure is provided in the fabrication of the SOI substrate, or both.
The disadvantageous distortions can be minimized by the inventively provided homogenization of mechanical irregularities (stresses) in the membrane layer and the free adjustability of the stress condition in general which this makes possible.
For homogenization, it is generally advantageous when the semiconductor layer is composed of an existing start layer of the SOI substrate and an additional reinforcing layer which is epitaxially grown onto the start layer, whereby the thickness of the reinforcing layer is selected such that the characteristics of the semiconductor layer as a whole with respect to the inhomogeneous stresses are predominantly determined by the reinforcing layer. With this method, a finished SOI substrate which is already provided as a basis for the membrane production can still be modified in the direction of the desired homogeneity, and the method is particularly suitable for rather thin start layers up to approx. 1 xcexcm.
A particularly advantageous development of this method provides that in the SOI substrate fabrication process, the insulator layer is recessed in the region of the support ring which remains when the membrane is later etched. This is based on the recognition that a substantial cause of the stress problems of the membrane is that the insulator layer itself likewise exhibits strong stresses. An insulator layer which remains in the region of the support ring, as has been common, thus exerts an adverse effect on the stress condition.
This can be advantageously accomplished simply by executing the mask for defining the insulator layer and the mask for defining the membrane in alignment with one another.
Another expedient possibility is to utilize an SOI substrate with a buried insulator layer that is generated by ion implantation in order to produce the locally limited insulator layer, because it would require appreciably more outlay to shadow the regions that should not be provided with the insulator layer particularly in connection with fabricating the SOI substrate in the wafer bonding method.
When the inventive method is a wafer flow process, it is also advantageous that layers serving for membrane definition are only deposited on the bottom side of the SOI substrate following the structuring of the semiconductor layer, because otherwise undesirable stress effects would emerge from these layers also.
Other advantageous developments and features of the invention, particularly with respect to the adjustability of the stress condition in general, are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating positionally exact surface-wide membrane masks, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.